| 摘要 |
PURPOSE:To shorten the arithmetic time by calculating high and low order bits concurrently, performing the arithmetic operation with respect to the presence/absence of carry from the low order bit and selecting the result of the high order bit arithmetic operation according to the carry of the low order bit. CONSTITUTION:Illustration is an embodiment applying the invention to an arithmetic circuit of 16 bits. Bits 0-7, the low order eight bits, are calculated by a whole adder with the technique the same as a conventional one. In terms of the presence or absence of carry from the low order eight bits, 8-15 bits, the high order eight bits, are concurrently operated. After the carry of the low order eight bits is decided, one of arithmetic results of the high order eight bits is selectively outputted according to the decision. In the circuit complying the invention, the arithmetic time is a one obtained by adding the arithmetic time for eight bits to the time required for selective outputting. Namely, the arithmetic time is a little more than half in the arithmetic circuit with conventional technique. It is no wonder that not only vertically bisecting the multibit arithmetic but also its multidivision offers the same effect.
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