发明名称 |
RESET DELAY CIRCUIT FOR AN ELECTRONIC POSTAGE METER |
摘要 |
<p>An electronic postage meter with a circuit to provide for a delay period before operation of a postage meter is disclosed. The circuit provides a fixed delay which is triggered when three input signals provided to the circuit become active. The input signals will be active in this embodiment to indicate satisfactory regulated voltage level, a satisfactory unregulated voltage level, and a satisfactory external clock frequency respectively. The output of the delay circuit upon acceptance of these active signals provides a reset delay signal to a system processor and also controls the signals that are provided to the non-volatile memories and the system printer. The circuit uses advantageously logic devices to provide the delay of the output signal rather than the traditional utilization of R-C network. The delay circuit is particularly useful in a system such as postage meter that utilizes a microprocessor and a non-volatile memory, to protect the contents of the non-volatile memory.</p> |
申请公布号 |
EP0194661(A3) |
申请公布日期 |
1987.08.12 |
申请号 |
EP19860103283 |
申请日期 |
1986.03.12 |
申请人 |
PITNEY BOWES INC. |
发明人 |
DIGIULIO, PETER C.;HAFNER, WARREN G.;STALZER, HENRY |
分类号 |
G06F1/24;G06Q50/00;G07B17/00;(IPC1-7):G07B17/02;G06F11/30 |
主分类号 |
G06F1/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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