| 摘要 |
PURPOSE:To attain high speed count while relieving load to a CPU in counting the sum or difference signal of input clock signals by selecting freely one operation among four kinds of operation as the count operation of two kinds of the input click signals based on a control signal from a selection circuit. CONSTITUTION:The 1st input signal CK1 is outputted by a latch circuit 21 and a one-shot circuit 24 synchronously with the 1st synchronizing signal phi1 and the 2nd input signal CK2 is outputted by a latch circuit 25 and a one-shot circuit 28 synchronously with the 2nd synchronizing signal phi1' whose phase is deviated from that of the signal phi1 and respective outputs P1, P2 are fed to a 2-way counter 30 as a count signal via an OR circuit 29. A prescribed level signal and one of the 1st and 2nd synchronizing signals are fed to the control element of the 2-way counter 30 by a selection means 31 as a control signal, which allows the 2-way counter to be counted. As the count operations of the 2-way counter, the additionor subtraction of the signals CK1, CK2, the addition count of the signals being the subtraction of the CK1 from the CK2, in total 4 kinds are selected.
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