| 摘要 |
PURPOSE:To prevent a data from being written erroneously, and to securely protect a memory data, by prohibiting a write after a write operation is completed even when a power source failure signal is significant while a CPU outputs a write signal. CONSTITUTION:When the write signal outputted by a CPU4 is H, and the output of an AND gate 5 is also H, the terminal Q output of a latch 12 goes to H, and in a period while the signal is H, the signal of H is added on an OR circuit 14 even when the output of an inverter 11 is inverted, therefore, the gate 5 is opened. Consequently even though a power source failure detection circuit 3 detects a power source loss in a timing when the write signal is H from a time t3 to a time t4, the output of the circuit 5 is kept at H up to the time t4, and for the time, the data is written normally. When the output of the circuit 5 changes from H to L at the time t4, the latch 12 is reset, and the output of the circuit 14 goes to L, therefore, the gate 5 goes to a closed state, and after that, the write operation on a memory 1 is prohibited.
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