| 摘要 |
PURPOSE:To shift from a lock state to a lock state at high speed and to stabilize a clamp control by providing a data flow discrimination part, a polarity discrimination part. A data synthesizing circuit and a data switching means and supplying the output of a D/A converter to a clamp circuit as a clamp control signal. CONSTITUTION:The output of an OR gate 14 analog converted by the D/A converter 10 is supplied to the clamp circuit 1. Thereby, the rough clamp control in the clamp circuit 1 is carried out, and a frequency/phase lock circuit 5 is guided to a locked state. In this case, even when the level of an input signal is situated at any position, and the amplitude of the input signal is small or large, the clamp control of either one of the flow discrimination part 12 and the polarity discrimination part 13 is functioned, so that the level of the input signal is rapidly led to a lock area. When the frequency/phase lock circuit 5 is shifted to the lock state, according to the operation of a fame pulse detection circuit 6, a clamp data processing circuit 9 or the like existing in the succeeding step thereof, the clamp control having high accuracy is performed.
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