| 摘要 |
PURPOSE:To decrease the frequency of contention of access to a buffer memory by providing independent buffer memories between two networks in packet transfer directions respectively, and connecting them so that the buffer memories are controlled by hardware almost completely. CONSTITUTION:A buffer memory (a) for transfer packets from a circuit control part 1 to a circuit control part 2 and a buffer memory (b) for opposite- directional transfer are provided independently of each other. Those have (n) plural segments which are independent in terms of hardware. Bus switching circuits 14-17 switch buses so that only one of the (n) segments can be accessed by the circuit control parts 1 and 2. A bus switching control part 18 performs the bus switching so that segments which become free are assigned to a transmission-side circuit control part 14 or 17 in order and packets in a memory are transferred to the transmission-side circuit control part in arrival order; and the reception-side control part and DMA controller when there is no empty memory or the transmission-side circuit control part and DMA controller when there is an empty memory inform a CPU so that they do not operate.
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