| 摘要 |
PURPOSE:To obtain a 'one over an odd number' frequency division circuit while keeping the advantages of two-phase clock control by providing a bypass circuit transferring a data to the next stage by clock under a prescribed condition while a clock controlled inverter (C-INV) is turned off by the control clock. CONSTITUTION:A bypass circuit (f) is connected in parallel with a C-INV(I3) in a conventional frequency division circuit, a FET 10 selects the output level of a C-INV(I2) and a transmission gate T1 uses a clock theta and outputs an inverted output of the C-INV(I2). The C-INV(I3) is turned off at timings t4, t10, t16, no write to a node D is applied but since the level of a node C is at a high level, the FET 10 is turned on. The timing writing by C-INV (I3, I4) is quickened by a half clock respectively at the timings t4, t10, t16, the operating period of a closed loop circuit is decreased by one clock to form the 'one over an odd number' frequency division circuit (1/3 frequency division circuit).
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