| 摘要 |
PURPOSE:To attain the digital conversion to a fine peak change and to decrease the phase difference between an analog signal and a digital signal by changing the logical value of the digital signal based on the change in the rugged state of a waveform of the analog signal. CONSTITUTION:A sampling signal (chi) sampling an analog signal (upsilon) in time series is outputted from a sample holding circuit 2. When the signal (chi) is inputted to the 1st storage circuit 5, the preceding sampling signal (chi) by one sampling period is outputted from the circuit 5 as a comparison signal (y). When the signal (chi) and the comparison signal (y) are inputted to a subtraction circuit 9, the difference of both the signals, that is, the difference of instantaneous values of analog signals (upsilon) at adjacent times is outputted as a change signal chi' from the subtraction circuit 9. When the change signal chi' is inputted to the 2nd storage circuit 6 of a comparison means 10, the preceding change signal chi' by one sampling period is outputted from the circuit 6. When the change signal chi' and a comparison signal (z) are inputted to a comparison circuit 11, a change difference signal chi'' in response to the difference between both the signals chi', (z) is outputted to a data terminal D of a flip-flop circuit 7 from the output terminal. That is, when the change difference is positive, the change difference signal chi'' is outputted, where logic 1 is outputted when the change difference is positive and logic 0 is outputted when it is negative.
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