| 摘要 |
PURPOSE:To generate a prescribed delay time even if a thin pulse is included by providing plural delay circuits, a counter, decoder and a gate circuit so as not to apply a forced reset. CONSTITUTION:Suppose that a count of a counter 32 is logical 1 when a pulse N1 comes, an output of a decoder 34 goes to a state (1), a delay circuit 10 is selected and the pulse N1 is impressed to the delay circuit 10. Further, an AND gate 20 is opened (decoder output is at an H level) to pass through an H level output produced by the delay circuit 10 after a prescribed delay time tau. The next pulse N2 comes while the pulse N1 is lost before this state is reached in this case. Since the count of the counter 32 is two and an output of the decoder 34 goes to a state (2) when the pulse N2 comes, a delay circuit 12 is selected to open an AND gate 22. The delay circuit 10 is not selected together with delay circuits 14, 16 (the state without any input pulse impressed) and the AND gate 20 together with AND gates 24, 26 is closed. |
