发明名称 CLOCK SIGNAL DELAY CIRCUIT
摘要 <p>PURPOSE:To allow the titled circuit to cope with a wide variety of input period and to attain the miniaturization by varying the time constant of the 1st monostable multivibrator and fixing the time constant of the 2nd monostable multivibrator. CONSTITUTION:An inverted output B of a monostable multivibrator 10 changes from a value '1' to a value '0' at a point of time when an input clock A fed to a clock input terminal 50 changes from a value '0' to a value '1' and the state of value '0' continues for a time T1 only decided by a capacitance of a capacitor 13 and a resistance value between a slider terminal (a) of a variable resistor 12 and a terminal (b) not connected to a power supply. An output (c) of a monostable multivibrator 11 changes from a value '0' to a value '1' at a point of time T1 when the inverted output B changes from a value '0' to a value '1', and the state of value '1' continues for a time T2 only decided by a capacitance of a capacitor 15 and a resistance value of a resistor 14. The capacitance of the capacitors 13, 15 and the resistance value of the variable resistor 12 and the resistor 14 are selected so that the times T1, T2 satisfy equation (1), (2), where T is a period of the input clock A.</p>
申请公布号 JPS62180606(A) 申请公布日期 1987.08.07
申请号 JP19860022517 申请日期 1986.02.04
申请人 NEC CORP 发明人 KUDO TOSHIYUKI
分类号 H03K5/13 主分类号 H03K5/13
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