发明名称 |
CONTROL SYSTEM FOR INPUT AND OUTPUT INSTRUCTION |
摘要 |
PURPOSE:To prevent deterioration of efficiency of a fast central processor by sending CC=2 back to the next input/output instruction even at a time point when the connection is not confirmed yet with an input/output device on an I/O interface on the same channel by the input/output instruction delivered precedently. CONSTITUTION:At the time of a central processing unit 10 delivers an input/ output start (SIOF) instruction to an input/output device 14 via a channel 13, the channel 13 starts an input/output action by an SIOF instruction that is delivered to an input/output device 15 via the channel 13 immediately before the SIOF instruction is delivered to the device 14. Thus it is displayed that a channel state register 23 is set under a channel communication mode as long as the SEL-OUT signal is equal to '1' even though the initial start sequence is presently carried out on an I/O interface and the OPL-IN signal is still kept at '0.' Thus a centralized control part 20 can give a report immediately to the unit 10 via a condition code setting signal 31. Then the unit 10 sets a condition code (=2) and can proceed to the next instruction processing. |
申请公布号 |
JPS62180447(A) |
申请公布日期 |
1987.08.07 |
申请号 |
JP19860021804 |
申请日期 |
1986.02.03 |
申请人 |
NIPPON TELEGR & TELEPH CORP <NTT> |
发明人 |
KOBASHI YOSHITSUGU |
分类号 |
G06F13/12;(IPC1-7):G06F13/12 |
主分类号 |
G06F13/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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