| 摘要 |
PURPOSE:To attain the generation of a master clock and a display clock with one clock generation circuit by providing a 2/5 frequency dividing circuit which inputs a signal from the oscillation circuit of 13.5mHz, and a horizontal synchronizing signal. CONSTITUTION:The signal of 13.5mHz inputted from a clock input 1 is 2/5-frequency divided, and the signal of 5.4mHz can be obtained. In such a case, 13.5mHz is represented as 858fH (fH:horizontal frequency), however, even when it is multiplied by 2.5, an integer is not obtained, and as a result, when it is left as it is, the phase of a display clock at every H is dislocated. Therefore, a set pulse generated from the horizontal synchronizing signal is inputted to the clear terminal of a 10 bit counter, and again a synchronization with a horizontal is taken. By constituting a circuit in such a way, a clock generation circuit where two PLLs are used is eliminated and the generation of the clock can be performed with one PLL.
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