| 摘要 |
PURPOSE:To perform real-time processing at a high speed in bulk, by supplying respective processors in a column with required results of prior-stage processors by applying the data bucket system. CONSTITUTION:Data inputted from data input terminal 8 are inputted to the 1st- stage column of processors 10 via parallel input processing circuit 26, and then processed in parallel. Then, processors 12 in the 2nd-stage column are supplied with required results among outputs of the prior-stage processors 10. Since data buses perform data transmission on the bucket interchange system between processors, the bucket interchange information of each processor is assigned according to arithmetic and the arithmetic processing is carried out successively up to the final stage. Consequently, the real-time signal processing can be performed at a high speed and in bulk and the output data of any processor in process of arithmetic is easily monitored. |
