发明名称 MASTER CLOCK CONTROL CIRCUIT FOR HIGH DEFINITION VIDEO REPRODUCING SYSTEM
摘要 PURPOSE:To rapidly lock in phase a master clock to a reproduction horizontal synchronizing signal by fixing an oscillation frequency before the phase lock of a PLL circuit is separated by a jitter generated in a reproducing compression video signal. CONSTITUTION:An output (rapid traverse reproduction command output) of high level obtained by an operation of a search switch 12, the first detection output detecting the lock separation of a disk servo circuit 9 and the second detection output detecting the lock separation of a jitter servo circuit 11 are inputted to an OR circuit 15. Accordingly, after the search operation or when a jitter component is large, a video disk player generates an OR output. According to this OR output, the PLL circuit for generating the master clock is brought into a fixed oscillation state. When the servo lock of the video disk player is separated, or when the search operation is performed, the master clock frequency is fixed to prevent a large lock separation of the master clock.
申请公布号 JPS62179290(A) 申请公布日期 1987.08.06
申请号 JP19860021576 申请日期 1986.02.03
申请人 SANYO ELECTRIC CO LTD 发明人 MORITA YOSHIHIKO;TOYAMA TAKEO;HIOKI TOSHIAKI;WATABE HIROSHI
分类号 H04N9/81;H04N9/89 主分类号 H04N9/81
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