发明名称 PROGRAM DEBUGGING DEVICE
摘要 PURPOSE:To attain the time control for the break function of a CPU by providing a timer control circuit where the target time and its working state are set, a comparator, a break address setting circuit,a break control circuit, etc. CONSTITUTION:A comparator 12 compares the address data supplied to a CPU 11 via an address bus AB with the break address set to a break address setting circuit 15. Thus a result comparison output signal S12 is outputted and inputted to a break control circuit 17 together with the control signal S16 received from a timer control circuit 16. Then the circuit 17 outputs the break signal S17 to the CPU 11 which is executing a program when the signal S12 is equal to the coincidence output and also the signal S16 is valid respectively. Thus the CPU 11 is broken. However the CPU 11 is not broken if the signal S16 is invalid. Thus the break action of the CPU 11 is controlled by the function of the circuit 16. Then it is possible to confirm whether the processing of the program is correct or not in terms of time. This secures the time control for the break function.
申请公布号 JPS62177640(A) 申请公布日期 1987.08.04
申请号 JP19860019479 申请日期 1986.01.31
申请人 TOSHIBA CORP 发明人 KOBAYASHI AKIRA;MORI HIDEO
分类号 G06F11/28 主分类号 G06F11/28
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