| 摘要 |
A semi-conductor decoder circuit includes 2N-1 circuits each formed of transistors vertically arranged in N stages, with the transistors of 2N-1, 2N-2 . . . 21, 20 number being disposed sequentially from the output stage in N stages in a tree structure. The gate width of the transistor at each stage is expanded as a distance from the output stage is increased so as to prevent an increase in ON resistance of the circuit and also to achieve a high speed operation.
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