| 摘要 |
PURPOSE:To correctly decode the contents of each bit data by following the timing of a read gate signal to a clock pulse and appropriately correcting it if the hourly interval of the clock pulse fluctuates within a permissible range. CONSTITUTION:The side of a control circuit 6 waits that the read gate signal rises to 'H'. After the rise is detected, the side repeatedly checks the binarization output of a binarization circuit 5 as long as 'H' continues. When the rise is detected, a detection flag is set. If the read gate signal is detected to fall from 'H' to 'L', the state of the flag is checked. Here a read gate signal generator circuit 8 transmits the hourly interval of the clock pulses before and after a counter 802 to a comparator 803. If the hourly interval of the clock pulse is decided to fluctuate within the permissible range, the timing of the read gate signal is appropriately corrected by following the clock pulse.
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