| 摘要 |
PURPOSE:To increase an information charge accumulation capacity formed on the side of a groove separation area and to efficiently integrate a memory device by connecting bit lines to a sense amplifier with the 1st and 2nd bit lines as a complementary pair. CONSTITUTION:The information charge accumulation capacity Cp is formed between a polycrystal silicon 3 on the side of the groove separation area 14 and an n<+> diffusion layer 5. When a word line 17 stands at an intermediate potential, the FETs of channels N and P are turned off, and recorded data in memory cells 18a-18d and 19a-19d is held. If the potential of the line 17 is made at 'H' or 'L', the cells 18a-18d or those 19a-19d are read and written. Accordingly bit lines 16a-16d and those 16e-16h are never simultaneously connected to the capacity Cp. One line is selected out of two sets of bit lines inputting sense amplifiers 15a-15d, whereby only one line 17 can pass through the area with one bit per cell. |
