| 摘要 |
PURPOSE:To increase the time capable of fetching of a CPU by storing data outputted from an error correction part in plural buffer memories by changing over in time division for a 1-vertical blanking period. CONSTITUTION:The serial/parallel conversion and error correction part 3 outputs the data after the error is corrected, a designation address on the buffer RAM 4I, 4II, an error correction processing completion signal (2) and a bus control signal (5). The error correction processing completion signal (2) forms a select signal (3) of a multiplexer 4i and a select signal (4) of a multiplexer 4ii through an inversion element 11 through an FF10 and the period for receiving the signal from the error correction part 3 and the period for receiving the signal from the CPU5 are shifted in time alternately with respect to the buffer RAMs 4I, 4II respectively. The buffer RAMs 4I, 4II are mutually shifted in timing by the 1-vertical blanking period and respectively operate by making 2-vertical blanking periods a cycle and the time capable of fetching of the CPU 5 is remarkably increased.
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