发明名称 INTEGRATION CIRCUIT
摘要 PURPOSE:To obtain an integration circuit having a time constant of 2N multiple without changing the capacitance of a capacitor and the current of a constant current source by using an up-down counter so as to control a multiplier and a switch circuit. CONSTITUTION:A multiplier 11 receiving an input signal, a capacitor 26 whose charging/discharging is controlled by a multiplier, a differential amplifier circuit 27 generating a bipolar output, a switch circuit 24 extracting switchingly the bipolar output, a comparison means 29 receiving the output of the said switch circuit and comparing it with the 1st and 2nd reference values, an up-down counter 23 whose up/down state is controlled by the output of the comparison means, a D/A converter 36 provided to the output of the up-down counter and an adder 25 to which the output of the D/A converter and the output of the switch circuit are supplied, are provided. The up-down counter controls the multiplier and the switch circuit and the level of both inputs to the adder is set nearly equally. Thus, the time constant is extended by 2N multiple.
申请公布号 JPS62176317(A) 申请公布日期 1987.08.03
申请号 JP19860018569 申请日期 1986.01.30
申请人 SONY CORP 发明人 YAMASHITA NORIYUKI
分类号 H02P25/04;H02P27/02;H03H11/04;H03K4/00;H03K6/00 主分类号 H02P25/04
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