| 摘要 |
PURPOSE:To ensure the continuation of a processing with a memory managing system without holding other devices while a certain device has a memory access, by using an arbitration circuit to arbitrate the access requests given from each bus system. CONSTITUTION:The 1st bus system 12 includes an address bus 14, a data bus 15 and a control bus 16. While the 2nd bus system 13 includes an address bus 17, a data bus 18 and a control bus 19. An access request signal 20 received from a CPU 1 is applied to an arbitration circuit 11 through a control bus 16 of the 1st bus system 12. Then an access request signal 21 received from a DMAC 2 is applied to the circuit 11 through a control bus 19. The circuit 11 performs the arbitrating actions in response to both signals 20 and 21 and sends the 1st and 2nd bus system queuing signals 22 and 23 showing the access permission or inhibition back to the CPU 1. |
