| 摘要 |
PURPOSE:To obtain the result of division with desired accuracy within a prescribed time by rounding a divisor after shifting it within the number of bits that can be processed by an arithmetic processor MPU. CONSTITUTION:When a divisor exceeds one word in case the words of the divisor that can be divided by an MPU is limited just one (16 bits), the divisor is shifted right by one bit so that the divisor is set within a single word. While a dividend is also shifted right by the same number of bits as those of the divisor. Both shifted divisor and dividend are rounded by means of the residue of the shift division that is consequently carried out by the shifts of the divisor and dividend. Then the MPU performs the division with use of the divisor and dividend undergone the rounding both in case the dividend is less than two words and in case the dividend exceeds two words respectively. Then the division processing is through after rounding the result of division to the nearest whole number. Thus it is possible to perform the division processing at a high speed after the desired arithmetic accuracy is secured. |
