发明名称 CIRCUIT FOR PREVENTING OVERCURRENT IN PARASITIC TRANSISTOR
摘要 PURPOSE:To prevent overcurrent and to prevent the breakdown of a semiconductor integrated circuit, by adequately setting the detecting level of a power-source-voltage detecting circuit, and fixing a substrate electrode to one potential of the power source voltage even if the power source voltage reaches a voltage, at which an overcurrent phenomenon is generated by a parasitic TRS. CONSTITUTION:A power-source-voltage detecting circuit 10 is constituted by insulated- gate field effect type transistors (MOSFET) 11-15 and an inverter circuit 16. The source of a P-type MOSFET 11 is connected to +VDD, which is a positive power source potential. The gate is connected to the drain. A short circuit 20 is composed of MOSFETs 21-25. The sources of the P-type MOSFETs 22 and 24 are both connected to +VDD. When the power source voltage VDD is lower than VDD0, the N-type MOSFET 21 is turned OFF and -VSUB and -VSS are separated. Thus the different potential is obtained. When VDD is higher than VDD0, the N-type MOSFET 21 is turned ON, and both become the same potential. Therefore, when the power source voltage reaches a value, at which an overcurrent phenomenon due to a parasitic TRS might be generated, a substrate potential is fixed to -VSS at a low impedance and the overcurrent phenomenon is prevented.
申请公布号 JPS62176155(A) 申请公布日期 1987.08.01
申请号 JP19860018671 申请日期 1986.01.30
申请人 SEIKO EPSON CORP 发明人 HASHIMOTO MASAMI
分类号 H01L21/822;H01L27/04;(IPC1-7):H01L27/04 主分类号 H01L21/822
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