| 摘要 |
PURPOSE:To supervise normalcy of data transfer by supervising the state of output signals of a flip-flop by a processor that transfers data serially synchronously with clock signals. CONSTITUTION:A processor 1 transfers data periodically. At first, the processor clears a shift register 7 and an RS-FF 9, and adds information of '1' prior to data and starts transferring. At a time when data of n-2 bit are sent, the state of RS-FF 9 is confirmed by an answer line 10, and when it is normal, the RS-FF maintains the state of '0'. When a clock made malfunction and excess pulse entered, it is set to '1' by the bit of '1' at the head of data. When normal, data of n-th bit are sent and it is confirmed that the RS-FF 9 is set to '1'.
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