| 摘要 |
<p>PURPOSE:To obtain a highly integrated memory cell array by arranging the prescribed number of memory cells in a matrix shape by forming a memory cell in an electrically erasable/rewritable memory transistor, and constituting the memory cell array by connecting a word line with a bit line. CONSTITUTION:The prescribed number of memory cells are arranged in the matrix shape by forming each of memory cells M11-M22 with one electrically erasable/rewritable memory transistor. And the memory cell array is constituted so that each control gate 1 of the memory cell transistor on the same line is connected to common word lines WL1 and WL2, and each drain D of the memory cell transistor on the same row is connected to common bit lines BL1 and BL2. In this way, it is possible to reduce an area per memory cell, and to make the memory cell array into the high integration, thereby the E<2>PROM of large capacity being realized.</p> |
