| 摘要 |
PURPOSE:To obtain a stable and accurate output by converting the edge part of a PCM signal including a jitter component to positive and negative pulses based on zero and feeding back the phase difference to a voltage controlled oscillator through a loop filter. CONSTITUTION:A digital signal S1 including a jitter component is delayed by a time corresponding to a half clock having a minimum repeat width 1/fmax of the signal S1 through a CR integrated circuit 6 and an inverter 7. Exclusive OR between this delays signal and the original signal S1 is operated to detect the edge part. The oscillation output of a voltage controlled oscillator VCO 4 has the frequency divided by a 1/N frequency divider 5 and has the timing adjusted by a timing circuit 9 so that the high level having a width 2fmax is equally divided into two by the trailing of the clock. The pulse in the edge part is equally divided into two by AND and inverter AND between outputs of the timing circuit 9 and an exclusive OR circuit 8. The difference of pulse width between positive and negative pulses is obtained by TTLs 12 and 13 and is fed back to the VCO 4 through a loop filter 2 and a DC amplifier 3. Thus, an accurate signal is reproduced stably. |
