发明名称 FORMATION OF MULTILAYER INTERCONNECTION
摘要 PURPOSE:To enhance insulating capability by a method wherein a first layer metal wiring is formed on an IC substrate, an insulating film is built by CVD and reactive ion etching to cover only the side walls of the first layer metal wiring, and an insulating film is formed by bias spattering to cover the entire surface. CONSTITUTION:A metal wiring 12 made of an Al-Si alloy is formed on an IC substrate 11 and, on the entire surface including the metal wiring 12, a PSG film 13 is formed by CVD. A process follows wherein reactive ion etching is performed for the etching of the PSG film 13, which continues against its entire surface until there is no PSG film 13 remaining on the horizontal surface of the IC substrate 11. After this process, some PSG film 13 is retained as side walls 13a on the sides of the metal wiring 12. Next, on the entire surface including the metal wiring 12 provided with the side walls 13a, an SiO2 film 14 is deposited by bias spattering. Another metal wiring is then formed on the SiO2 film 14. This method prevents the shoulders of the first metal wiring from exposure and improves the surface geometry of steps to be produced over the first metal wiring 12.
申请公布号 JPS62172740(A) 申请公布日期 1987.07.29
申请号 JP19860013727 申请日期 1986.01.27
申请人 OKI ELECTRIC IND CO LTD 发明人 NAKAMURA HIROKI;FUSHIMI KIMIHISA
分类号 H01L21/3213;H01L21/31 主分类号 H01L21/3213
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