| 摘要 |
PURPOSE:To simplify a data setting by constituting a circuit with a data output means to which the remaining part of an address bus used as a data bus is connected, and to which a data is inputted with the timing of an output signal outputted from an address decode means. CONSTITUTION:When a CPU 1 writes the data on an output port 2, an address is outputted to address buses A0-A15 in the first clock cycle T1. In the second clock cycle T2, and I/O port selection signal, the inverse of IORQ, and a write signal, the inverse of WR, go to L levels, and the output signal, the inverse of X, of an address decoder 3 to the L level, and a clock input terminal, the inverse of CK of the output port 2 to the L level. Afterwards, in the fourth clock cycle T4, when the I/O port selection signal, the inverse of IORQ, and the write signal, the inverse of WR, go to H levels, the signal of the clock input terminal, the inverse of CK, in the output port 2 changes from L to H. And the output port 2 latches the values of input terminals B0-B15 at that time as the data with the timing of the leading of the signal. In this way, the execution time of a program and a program capacity can be reduced. |
