| 摘要 |
PURPOSE:To prevent the lowering of a processing capacity by providing a data cache which stores a part of data provided within a central processor by every block unit, and a reference change information buffer which stores a part of R bits and C bits provided within the central processor. CONSTITUTION:A data cache 6 which stores a part of the data within a main memory data storage part 2 by every block unit,and a reference change information buffer 7 which stores a part of the R bits and the C bits within a main memory key storage part 3 are provided. When an instruction RRB is issued from an arithmetic unit 9, an R and C bit changing means 19 outputs a changing means 19a by detecting a coincidence at a comparator 14 or 15, and makes an R bit 22 in a coincided entry 13 to 0, on the other hand, it sends a C bit 23 and the R bit 22 before a change in the entry 13 to the arithmetic unit 9 through an R and C bit register 17. Therefore,the states of the R bit 22 and the C bit 23 corresponding to a page frame are reflected to the condition code of the instruction RRB. I this way, the lowering of a processing capacity in a virtual memory system can be prevented.
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