| 摘要 |
PURPOSE:To decrease the data transfer delaying when the data is transferred between an input I/O port and an output I/O port through a memory by providing an up and down counter, an inverter and a gate circuit. CONSTITUTION:When the data inputted through a memory 3 to an input I/O port 1 are transferred to an output I/O port 2 by a direct memory access (DMA), first, input data are accommodated to the memory 3. Next, when the data are outputted by the DMA transfer between the port 2 and the memory 3 and the number of input data and the number of output data are coincident, the output of an up and down counter 6 comes to be a logic '1' and the output of an inverter 7 comes to be a logic '0'. Thus, an AND gate 8 prohibits the data transfer between the memory 3 and the port 2 and the number of times of the transfer between the port and the memory is suppressed so as not to exceed the number of times of the transfer between the port 1 and the memory 3. Thus, by limiting the number of times of the DMA data transfer between the port 2 and the memory 3 and preventing an empty sending, the data transfer delaying can be decreased. |
