| 摘要 |
PURPOSE:To eliminate a wasteful cycle at the time of data transfer and to speed up the data processing by adding and sending a transferer designating code to an address bus, and adding and sending a transferer code to a data bus. CONSTITUTION:When a device 2 sends an address to add the designating code of a transferer to an address bus 5 and the data to add a transferer code to a data bus 6, a device 1 coincident to the transferer code sends the data of the designating address on the data bus 6. Devices 3 and 4 coincident to the data transferring code fetch the data to the internal part, after all data are stabilized, the transfer of respective devices is completed by making an acknowledging signal 9 'High'. Thus, for the fetching timing of the data, the rise of the signal 9 is made suitable, reading and writing can be executed in the same cycle and the writing to plural devices can be executed. Namely, the wasteful cycle at the time of the data transfer is eliminated and data processing can be speeded up. |
