| 摘要 |
The circuit for detecting synchronism in a digital broadcast receiver comprises series-parallel converters (20,21) receiving respective synchronisation word outputs (25,31) of a 4-phase PSK demodulator; conversion means (26-31; 33-37) for making all the series-parallel converter outputs high level; and 1st and 2nd AND gates (38,39) which receive series-parallel converter outputs and whose outputs are supplied to an OR gate (40). Input to the 1st AND gate is a combination of the odd-numbered bits in the output of one series-parallel converter and the even-numbered bits in the output of the other series-parallel converter, while the 2nd AND gate's input consists of the other output bits of the converters. |
