发明名称 Latch-up resistant CMOS structure for VLSI including retrograded wells
摘要 A complementary metal oxide semiconductor (CMOS) structure having the source and drain regions of individual transistor devices separated from the peak impurity concentrations of the respective N- and P-wells of such devices. The CMOS structure includes trenches between the individual transistor devices, and highly doped field regions are formed in the bottom of the trenches. Each N- and P-well includes a retrograde impurity concentration profile and extends beneath adjacent trenches.
申请公布号 US4683488(A) 申请公布日期 1987.07.28
申请号 US19860835447 申请日期 1986.02.28
申请人 HUGHES AIRCRAFT COMPANY 发明人 LEE, WILLIAM W. Y.;CHANG, KUANG-YEH
分类号 H01L27/092;(IPC1-7):H01L27/02 主分类号 H01L27/092
代理机构 代理人
主权项
地址