| 摘要 |
PURPOSE:To attain optionally the simple connection of additional processors and to reduce the hardware quantity with high reliacility, by providing a sequence controller of a microprogram MP only to a master processor for execution of the MP of the additional processor. CONSTITUTION:A register 11 which reads out the contents of the MP of a master processor 1 serves as a memory address generator used for highly efficient execution of memory access as well as a sequence control part. While a register 21 which reads out the contents of the MP of an additional processor 2 instructs pipeline arithmetic processing in the processor 2 as an extended field of the register 11. A controller 12 of the processor 1 applies a decided microaddress to a memory device 10 as well as to the memory device 10 of an additional processor 2. As a result, the processor 2 executes processes A' and B' in steps S211 and S212 in response to a fact that the processor 1 carries out processes A and B in steps S111 and S112 respectively. Thus multiplex array processing is possible as a whole.
|
