发明名称 BUS CONTROL SYSTEM
摘要 PURPOSE:To improve the DMA processing capacity by performing the switch in a dynamically set ratio between the bus conflict control that stops a processor and acquires the bus use right and the conflict control that acquires the bus use right after the end of a cycle. CONSTITUTION:A device which performs the bus conflict control to acquire a bus after stopping a processor when a DMA request is received serves as the 1st bus conflict means 15. While a device which performs the bus conflict control after the end of a memory cycle of the processor serves as the 2nd bus conflict means 16. These two means 15 and 16 are switched with control by a switching means 14 in response to a ratio set by a ratio setting means 17.
申请公布号 JPS62168253(A) 申请公布日期 1987.07.24
申请号 JP19860009544 申请日期 1986.01.20
申请人 FUJITSU LTD 发明人 KISHINO TAKUMI;HASHIMOTO SHIGERU
分类号 G06F13/30;G06F13/28;(IPC1-7):G06F13/28 主分类号 G06F13/30
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