发明名称 SYNCHRONOUS CLAMPING CIRCUIT
摘要 PURPOSE:To narrow a band of a noise component which is detected at the time of a clamp operation, by executing the clamp operation by a clamp pulse which has lowered a sampling rate by a frequency dividing circuit. CONSTITUTION:A video signal Sin which has been reproduced by a VTR is supplied to a clamping circuit 10 from an input terminal 1, and also, supplied to a synchronization separating circuit 2. A horizontal synchronizing signal which has been brought to a synchronizing separation by the synchronization separating circuit 2 is applied to a clamp pulse generating circuit 3, in which a clamp pulse CP0 is generated by a timing corresponding to a sync chip part of the video signal Sin. This clamp pulse CP0 is brought to a/n frequency division by a 1/n frequency dividing circuit 4, and applied to the clamping circuit 10. In this way, the band of a noise component which is brought to sample holding at the time of a clamp operation is narrowed to a/n of the case when clamping is executed at every 1H, and the noise resistance is improved.
申请公布号 JPS62168470(A) 申请公布日期 1987.07.24
申请号 JP19860009713 申请日期 1986.01.20
申请人 SONY CORP 发明人 AKATSUKA HIROMICHI;FUKUDA TOKUYA
分类号 H04N5/18 主分类号 H04N5/18
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