| 摘要 |
PURPOSE:To make the titled circuit applicable to an input signal ranging over a wide frequency range, by switching or changing the frequency generated by a reference frequency generating means so that a DPLL circuit can be clocked to an input signal when an out-of-synchronism detecting means detects the out of synchronism of the DPLL circuit. CONSTITUTION:The 1st loop is composed of a phase comparing means 3, variable frequency dividing means 2, and a feedback path 5 which feeds back the output of the means 2 to the input of the phase comparing means 3. The 2nd loop is constituted of the phase comparing means 3, an out-of-synchronism detecting means 4, a reference frequency generating means 1, the variable frequency dividing means 2, and the feedback path 5 which feeds back the output of the means 2 to the input of the phase comparing means 3. When the out-of- synchronism detecting means detects that a state where the 1st loop is not locked continues, the 2nd loop switches or changes the output frequency of the reference frequency generating means 1 in accordance with the direction, in which the frequency of an input signal is deviated from the 1st loop locking range, so that the 1st loop can be locked to the frequency of the input signal. |
