发明名称 UP-DOWN COUNTER
摘要 PURPOSE:To reduce the number of elements used in an up-down counter including decoder and, at the same time, to make the up-down switching operations of the counter easier, by constituting the (2XN)-notation up-down counter by combining a binary counter composed of one stage of T-flip flop and an N- notation Jonson counter. CONSTITUTION:A decimal (2X5) up-down counter is constituted of a binary counter composed of a T-flip flop 11 and a quinary counter composed of three D-flip flops 12-14. Clock signals CLOCK to be counted are inputted to the T-terminal of the T-flip flop 11 and each one terminal of three-input AND gates 15 and 16. The output of the binary counter is inputted to the N-notation counter where the output is counted and outputs of both counters are inputted to a decoder and, for example, numerical data of BCD are obtained. Switching between the up-counting and down-counting is performed by the Jonson counter. Therefore, many elements are not required for switching.
申请公布号 JPS62166617(A) 申请公布日期 1987.07.23
申请号 JP19860008476 申请日期 1986.01.17
申请人 SANYO ELECTRIC CO LTD 发明人 NAKAMURA TADAO
分类号 H03K23/00;G06F7/62;H03K23/86 主分类号 H03K23/00
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