| 摘要 |
PURPOSE:To reduce the ripple of an analog voltage output to prevent the responsiveness of said voltage, by shortening the word lengths of digital numerical data added to a pulse width modulator for high-order bits only and the periods of PWM outputs. CONSTITUTION:A digital numerical data output 14 is connected with one input A of an adder 15 and the added output (A+B) 16 is divided into a high-order bit part 17 and low-order bit part 18. The low-order bit part 18 is fed back to the other input B of the adder 15 through a temporarily holding register 19. A pulse width modulator 1 which forms a PWM output 22 which is modulated in pulse width in accordance with the numerical data of the higher-order bit part 17 is provided and those which are functionally equivalent to conventional examples are adopted. Furthermore, by shortening the word lengths of the digital numerical data added to the pulse width modulator for the high- order bits only, the period of the PWm output is made shorter. In addition, by realizing a constitution which repeatedly adds the low-order bits that are set to a cut-down state in the above-mentioned processes to the original digital numerical data under an accumulated condition, high resolution is simultaneously obtained.
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