| 摘要 |
PURPOSE:To synchronize again in a short period and eliminate data destruction of display memory by inputting reset signals generated by external synchronizing to the second display count circuit and continuing to input reset signals to the first display count circuit until discordance of phase continues. CONSTITUTION:External synchronizing signals 20 from an external synchronizing circuit 2 are inputted to a horizontal counter 43 and a vertical counter 44 through OR circuits 49, 50. Accordingly, even when input of horizontal and vertical reset signals 47a, 48a, which are input of one OR circuit, is not generated, the signals are supplied to reset input terminals of a display cycle counter circuit 42, a horizontal counter circuit 43 and a vertical counter circuit 44. Count output of counters 42-44 is reset to initial state. However, as another display cycle counter 41 is not reset forcibly by the external synchronizing signals, it continues counting of clock signals 10 unlike other counter circuits.
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