| 摘要 |
PURPOSE:To surely obtain 2/5 divided output even when horizontal synchronizing signals cause jitter by composing all pulses by NAND gate circuit and making the pulse that clears a 10 bit counter only one. CONSTITUTION:A pulse of one clock generated in the rising part of horizontal synchronizing signals is prepared by latch circuits 13, 14 and a NAND gate circuit 12, and inputted to a clearing terminal of a 10 bit counter 1, and at the same time, positive phase clock is inputted as a clock. A pulse held between the fourth bit and fifth bit of the positive phase clock and a pulse held between the nineth bit and tenth bit are prepared in NAND gate circuits 7, 8 using positive phase and first bit and the second bit and a pulse held between the sixth bit and seventh bit of the opposite phase clock are prepared in NAND gate circuits 9, 10 by latch circuits 3-6 using positive phase output and opposite phase clock. All of these pulses are composed by an NAND gate 11 and 2/5 frequency divided output is obtained.
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