| 摘要 |
PURPOSE:To surely evade a flaw in control operation due to the abnormality occurrence of a CPU, to perform high-reliability control operation, and to simplify the constitution by using plural CPUs for control operation which store programs having the same contents. CONSTITUTION:The CPUs 2a-2d which control an input/output device 1 store the programs with the same contents and the device 1 outputs a driving signal in response to access signals from the respective CPUs and also outputs a data set ready signal in response to data request signals. Then, if the CPU 2a for control outputs a trouble occurrence signal, the CPU 2b outputs a data request signal to a switching control circuit 5, which closes a gate in response to disable a shift register to operate and also outputs a gate signal to an interface circuit 5b to open gates for an address bus, a data bus, and a control line. Consequently, the CPU 2b transfers specific data to the device 1 and specific control operation is carried on by being backed up by the CPU 2b.
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