| 摘要 |
<p>PURPOSE:To improve data transfer efficiency by flag bit synchronism by providing a memory for data transfer which can be accessed directly from outside regardless of the instruction execution of a processor in the processor. CONSTITUTION:The processor 1 executes instructions including a data readout instruction, but no flag bit is set as to data 1 and 2. Namely, no data is transferred to the memory 11 from outside, so the same program address is loaded in a program counter 14 from a decoder 16 and the instruction is executed again. When flag bits are set after data 3 is read out, this data 3 is read out of a specific address area of the memory 11 to a computing element 13, which performs arithmetic operation. Thus, the execution of the readout instruction for all data is completed and then respective bits constituting flag bits 12 are reset.</p> |
