发明名称 |
SUBSTRATE VOLTAGE GENERATING CIRCUIT |
摘要 |
PURPOSE:To apply the operation margin test over a wide range by stopping the operation of a charge pump circuit only at wafer test. CONSTITUTION:A potential of a pad 8 is brought into a GND level at wafer test to turn of a FET 7. When a phi signal from an OSC 1 goes to a VCC level and a node N1 reaches an H level, the node N2 is charged instantly to a (VCC- VT) level and the node N1 is kept to the VCC level. When the phi signal goes to L, the node N1 goes to a GND level and no signal is transferred from the node N1 to a VBB level. The cycles above are repeated and no electron is injected at test.
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申请公布号 |
JPS62165791(A) |
申请公布日期 |
1987.07.22 |
申请号 |
JP19860008579 |
申请日期 |
1986.01.17 |
申请人 |
MITSUBISHI ELECTRIC CORP |
发明人 |
MIYATAKE HIDEJI;FUJISHIMA KAZUYASU;KUMANOTANI MASAKI;HIDAKA HIDETO;DOSAKA KATSUMI;KONISHI YASUHIRO |
分类号 |
G11C11/408;G11C11/34;G11C11/401;G11C29/00;G11C29/50 |
主分类号 |
G11C11/408 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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