| 摘要 |
PURPOSE:To eliminate an output noise by inserting a latch circuit having a hysteresis characteristic in its input/output characteristic between an output signal line supplied with an intermediate potential and a circuit receiving a signal on the output signal line. CONSTITUTION:Plural blocks of the same constitution each having a memory cell 1 are provided and each block is selected by an address signal given externally. A latch circuit having a histeresis characteristic in its input/output characteristic, that is, a Schmitt trigger circuit 39 is inserted between an output data bus 14 and an output buffer 15. The bus 14 is kept to an intermediate potential during a period T in response to an intermediate potential control signal 20 and an output of the circuit 39 keeps the preceding state during the period T. When the bus 14 is released from the intermediate potential and the next data is given thereto, an H or L level is given to the read data and the circuit 39 inverts its input level to give the result to the output buffer 15.
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