| 摘要 |
PURPOSE:To decrease the number of elements of a data register by constituting the data register of a shifting register circuit controlled by a two-phase clock signal, and providing a logical circuit to transfer the data to the shifting register circuit only when an address designating signal is in an activated condition. CONSTITUTION:When an address designating signal 7a comes to be 'H' and comes to be an activated condition, clock signals phi3a and phi4a of signal lines 42 and 43 come to be the same signals as clock signals phi3 and phi4 and to the input part of a registering circuit 24a, accommodating data are transferred. After 8 cycles of the clock signals phi3 and phi4, a shift registering action is completed. While the address designating signal 7a is a 'L' condition, namely, when it is inactive, the signal line 43 is fixed to 'L', the signal line 42 is fixed to 'H', a signal line 44 is also fixed to 'L', the shift registering action is not executed and the accommodating data stored already are maintained at a latch circuit composed of MOSFET 29 and inverters 32 and 33. |
