发明名称 DELAY CIRCUIT
摘要 PURPOSE:To function an automatic gain control loop, and to output a delay output signal of which the signal level is stabilized, by detecting a difference between input/output levels in an analog delay line, and controlling the gain of a variable gain amplifier. CONSTITUTION:A reproducing luminance signal is clamped at a clamping circuit 2, and is supplied to a CCD delay line 4 which gives a delay quantity of 1H+ nbit, and a delay line 5 which gives a delay quantity of nbit. A signal subtractor 6 detects a stroke component, and a signal subtractor 8 outputs a reproducing luminance signal from which a cross talk component is eliminated through a voltage controlled type variable gain amplifier 9. A clamping circuit 12 clamps a 1H delay signal supplied through a voltage controlled type variable gain amplifier 12, and supplies it is a level comparator 13, and the level comparator 13 performs a gain control for voltage controlled type variable gain amplifiers 11 and 9 with a compared error output between the clamping circuits 2 and 12, and always makes coincident with the signal level of the input and the output of the CCD delay line 4.
申请公布号 JPS62164398(A) 申请公布日期 1987.07.21
申请号 JP19860005116 申请日期 1986.01.16
申请人 SONY CORP 发明人 FUKUDA TOKUYA;AKATSUKA HIROMICHI
分类号 H03H11/26;H04N5/93;H04N5/94;H04N9/84;H04N9/87;H04N9/88 主分类号 H03H11/26
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