| 摘要 |
PURPOSE:To uniformly correct a signal and to avoid a signal with a sufficient long time width, which does not require correction, from being corrected by setting a value obtained by majority decision from continuous (m+1)-bits of an input picture signal and continuous m-bits of a corrected output picture signal to an output correction picture signal. CONSTITUTION:The titled circuit is provided with the 1st accumulation circuit 1 continuously accumulating (m+1)-bits of an input picture signal string PIX (here, 4) in synchronization with a clock signal CLK, the 2nd accumulation circuit 2 accumulating m(3)-bits of an output picture signal string OUT and a majority decision arithmetic circuit 4 taking the all bits (7) of the accumulation circuits 1 and 2 for an input. The output of the majority decision arithmetic circuit 4 is latched by a type D flip flop 5, and transmitted as the output picture signal OFF. If '1' is inputted to zero continuity by three bits in a row, it is corrected to '0'. when '1' is inputted to zero continuity by four bits or more in a row, '1' appears in the output picture signal by the bit length. The majority decision arithmetic is uniformly applied to both logics '1' and '0', and there is no concern that validity is decided only by one logic value.
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