发明名称 CFET inverter having equal output signal rise and fall times by adjustment of the pull-up and pull-down transconductances
摘要 A circuit comprises P-channel and N-channel field effect transistors. A conduction electrode, such as a drain, of one of the transistors is coupled to a conduction electrode of the other transistor. Means are provided for ensuring that the currents in the transistors when changing state, and hence the rise and fall times of an output signal of the transistors, are substantially equal. Preferably, the ensuring means comprises the channel length of the P-channel transistor being smaller than that of the N-channel device. Alternately, either the doping level or the width of the P-channel device can be greater than that of the N-channel device.
申请公布号 US4682055(A) 申请公布日期 1987.07.21
申请号 US19860839917 申请日期 1986.03.17
申请人 RCA CORPORATION 发明人 UPADHYAYULA, LAKSHMINARASIMHA C.
分类号 H01L27/06;H03K19/003;(IPC1-7):H03K17/687 主分类号 H01L27/06
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