发明名称 SIMULATING DEVICE FOR SUBSCRIBER SYSTEM
摘要 PURPOSE:To surely carry out a general test on an inter-trunk circuit terminal equipment test adapter by giving a delay on a par with the case where a sub scriber line terminal equipment is viewed from an exchange side, folding an information bit expressing the signal of an information message as it is and folding a control bit after it is converted into any values. CONSTITUTION:An PM decoder circuit 11 and an PM encoder circuit 16 are provided, between which AND gates 12 and 12', OR gates 13 and 13', a switch 17 capable of switching the outputs of signals '1' and '0', a state bit specifica tion switch group 18 which switches the control bit to any values so as to fold, a delay circuit 14 on a par with an OCE using a clock of 4mHz, and a delay circuit 15 equivalent to an SLT obtained by subtracting a delay amount in the OCE with the aid of a clock of 8mHz are provided. The information bit is folded as it is, whereas the control bit is converted into any values within a fixed range. Therefore such a general test on an OCE test adapter can be surely carried out that the trouble of a state bit detector in the OCE test adapt er and that of the set place of the control bit are pinpointed.
申请公布号 JPS62164354(A) 申请公布日期 1987.07.21
申请号 JP19860006760 申请日期 1986.01.16
申请人 FUJITSU LTD 发明人 OZAKI TAKAYUKI
分类号 H04M3/26 主分类号 H04M3/26
代理机构 代理人
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